The present invention relates generally to the field of video displays and more particularly to an improved raster engine with a multiple adapting display interface.
Video displays are used in computer systems to present visual images to a user based on video data provided by a computer or other processing device. The display allows a user to effectively receive information from and to interact with application programs running in the system. Such computer systems and displays are employed in numerous business, consumer, entertainment, and industrial settings, including automated industrial control systems.
Displays are available in a variety of forms, such as color or monochrome, flat panel, liquid crystal display (LCD), electro-luminescent (EL), plasma display panels (PDP), vacuum fluorescent displays (VFD), cathode ray tube (CRT), and may be interfaced to a computer system in analog or digital fashion. The display is provided with video data frame by frame, which is scanned onto the display screen according to a scanning method which may include progressive scan, dual scan, interleave scan, or interlaced scanning. The cost of displays varies with the display resolution and quality. For example, color displays generally cost more than monochrome displays. The number of pixels, as well as the number of available colors per pixel (bits per pixels) also affects display cost. The cost of a computer display may be a large percentage of the overall computer system cost. As the application of computer system displays varies greatly, displays are accordingly provided in a variety of price ranges.
Interfacing between a computer or other processing device and a display is ordinarily accomplished using a video controller, also variously referred to as graphics adapter, graphics controller, video display adapter, display controller, and display adapter. The screen resolution on a PC is determined by the video controller, which may be plugged into one of the computer""s expansion slots. In conventional systems, the display must also be able to adjust to the resolution of the video controller. Common video controllers come with their own drivers for an operating system, which are installed after the video controller is installed. The driver allows the operating system to display its video output at a certain number of resolutions and colors. The video controller may include a raster engine which rasterizes video data from a frame buffer into a format that the display can accept for rendering to a user.
Some typical display screen resolutions include 640xc3x97480, 800xc3x97600, 1024xc3x97768, 1280xc3x971024, and 1600xc3x971200, expressed in terms of the number of columns and rows (lines) of bits on the display screen. Higher resolutions can be used to display larger images or to show more detailed images, depending on the number of pixels per inch (ppi) and the distance of the user from the screen. In addition to display resolution, the number of colors that can be displayed varies from 2, to 8, to 16, to 256, to 65 thousand, up to 16 million. Although high-end video controllers can provide maximum colors at maximum resolution, there is typically a tradeoff involving memory and bus bandwidth, wherein the higher the resolution, the fewer the available colors. With the wide variety of available display types, and the associated cost variance, there is a need for improved video controllers which are easily adaptable to interface the display requirements of computer system applications with a plurality of disparate display types, allowing a single video controller to be used in a variety of computer systems of various cost requirements.
In addition, where a computer system application is particularly cost sensitive, a lower cost monochrome display may be selected, such as a Super Twist Nematic (STN) LCD display. In environments that require high temperature operation, it may be beneficial to use an EL display. In many such displays, it may be desirable to employ pixel dithering techniques in order to represent a variety of shades of gray or colored shades. Such grayscale dithering may improve the visual image presented to a user by selectively energizing and de-energizing certain pixels according to a dithering algorithm or scheme. This may be particularly effective when employed with display types where each pixel has only two states, e.g., an xe2x80x98onxe2x80x99 state and an xe2x80x98offxe2x80x99 state. Conventional techniques, however do not allow flexible application of grayscaling to multiple disparate display types in a single video controller. Thus, there is a need for improved video controllers having easily adaptable grayscaling functionality which may be employed in association with a plurality of disparate display types.
Images on a display may be overlayed with a cursor image in order to facilitate user interaction with an application program and/or an operating system. The cursor image may be superimposed on the displayed image by computer system software or by the video controller. Using the video controller to overlay a cursor image on a displayed image is difficult in association with a dual scanned display, where the upper and lower portions of the display screen are scanned in parallel. Cursor overlaying is particularly difficult where the cursor image location crosses the boundary between the upper and lower portions of the display. Software cursor overlaying techniques occupy system resources and processor time, which may be unacceptable or undesirable in some applications. Hence, there is a need for improved cursor overlaying apparatus and methodologies, particularly for use with dual scanned displays.
Blinking objects or portions thereof may be presented on a computer display, to indicate special conditions or to otherwise accentuate a video feature. Software blinking techniques have thusfar been employed to effectuate blinking characters and display features on bitmapped displays. However, the use of software occupies computer system processor time and may consume additional memory and other resources. In addition, blinking of individual pixels, as opposed to character blinking, is burdensome using conventional techniques. Thus, there is a need for improved display blinking apparatus and methods which provide for pixel blinking and which reduce or minimize the overhead and possible memory usage associated with conventional bitmapped display blinking techniques.
Conventional video controllers are sometimes tested during manufacturing, to ensure proper operation prior to shipment to an end user or retailer. This testing typically involves applying a known set of video input data to the video controller and obtaining an output data set, known as a video signature. This signature is then analyzed using a signature analyzer to determine whether the video controller is operating properly. However, where the display image includes changing pixels, such as time, date, or other information which varies as a function of time, conventional signature analyzers may indicate a failed signature comparison, even where the video controller is operating properly. In addition, conventional video signature analyzers are expensive, and require extensive programming and user knowledge in order to operate. Moreover, the conventional signature analyzers may not be easily employed to test video controllers installed in a customer computer system. Thus, there is a need for improved video signature analyzers and video controllers which provide for verification of proper operation in association with changing video displays, and which provide for self-testing in a user computer system.
Raster engines typically obtain image data from a frame buffer in memory via a bus, wherein the frame buffer may be in main memory or in a separate display memory. The bus may provide access between the raster engine as well as between other devices in a computer system. Thus, there are situations in which the raster engine requires display image data from the frame buffer, and yet the raster engine cannot timely obtain such data due to contention with other devices using the common or shared bus. Thus, the raster engine may become empty, for example, during excessive bus loading conditions. In this case, the video display interfaced by the raster engine may exhibit undesirable visual effects under these conditions. For example, the display may suffer from visual defects such as jittering, shifting, flashing, and blank-outs in the displayed video image. Thus, there is a need for improved methods and apparatus for preventing or minimizing empty raster engine conditions, and the undesirable display effects associated therewith.
The foregoing and other shortcomings associated with conventional video controller devices and methodologies are reduced or minimized by the present invention, which provides a video controller and raster engine which is easily programmed to interface a computer system running a variety of application programs with a plurality of disparate display types. The invention may thus be employed in high end as well as highly cost sensitive computer system applications in association with displays ranging from high definition television (HDTV) to low resolution monochrome EL and/or LCD display panels. The invention provides for software programmable registers in the video controller raster engine by which a user may programmatically adapt or configure the raster engine to provide video data to a wide variety of different displays with different color capabilities and resolutions. In addition, programmable grayscaling is provided, together with hardware cursor features applicable to dual scan displays, and hardware blinking apparatus providing low overhead blinking on an individual pixel basis. Moreover, the invention provides for integrating a video signature analyzer in the video controller, providing for self-testing, as well as the capability of testing video signatures for displays having changing portions.
In accordance with one aspect of the invention, there is provided a video controller for interfacing a frame buffer to a display in a computer system, which comprises a raster engine adapted to receive video data from the frame buffer, to format the video data, and to render the formatted data to a display, as well as an integral bounded signature analyzer. The bounded signal analyzer is adapted to analyze the formatted data from the raster engine in whole or in part, allowing a signature to be taken, for example, on any rectangular area within an image. Thus, areas of a screen containing changing images may be selectively avoided. In addition, whereas conventional unbounded signature analyzers provide only pass or fail indications based on signature comparison, the analyzer of the present invention allows finer grain identification of where a problem occurs.
For example, testing four quadrants of a display separately allows isolation of an image problem to a specific quadrant. In this regard, a portion of the formatted data from the raster engine may be bounded by first horizontal and vertical values corresponding to a first location on the display, and second horizontal and vertical values corresponding to a second location on the display, wherein the signature analyzer is adapted to provide a signature indicative of the portion of the formatted data. These first and second horizontal and vertical values are programmable through the use of one or more control registers via the host computer system.
Integration of the signature analyzer with the raster engine, moreover, enables regression testing of video simulations during various manufacturing steps where a separate signature analyzer may not be otherwise available. In addition, the integral signature analyzer may be used for periodic or operator initiated self-testing of the video controller after the device has been shipped to an end user and/or a retailer. The invention thus provides significant advantages over conventional signature analyzers and video controllers through the bounded nature of the signature analyzer as well as by the integration thereof with a raster engine.
The signature analyzer may further comprise a linear feedback shift register (LFSR) adapted to receive parallel input data (e.g., 24 bits), and further to provide a signature output indicative of the parallel input data. This provides testing time advantages over previous signature analyzers, wherein video data was obtained serially. In addition, the LFSR may be adapted to provide a non-zero signature output in response to zero parallel input data, through the use of a logical inversion in the LFSR chain.
The video signature analyzer is further programmable through the use of one or more control registers accessible to the host computer system, whereby test initiation and definition/adjustment of the bounded display areas to be tested is controlled by a computer system user and/or an application program running on the system. For example, self-testing may be initiated as part of a startup application program to verify proper video controller operation before proceeding to run one or more application programs. This may be advantageously employed, for example, in industrial control applications wherein the display of safety related information is desired. Once proper video controller operation is verified, the video signature analyzer can also be used to test other system functions such as graphics operations or DMA memory operations. This is done by manipulating a target image and then taking a signature of the image as it passes to the display.
In accordance with another aspect of the invention, there is provided a video controller for interfacing a frame buffer to a dual scan display having adjacent first and second display portions with a display boundary therebetween, such as a dual scan display. The video controller comprises a raster engine adapted to receive video data from the frame buffer, to format the video data, and to render the formatted data to the dual scan display line by line, as well as a hardware cursor adapted to selectively overlay a cursor image onto one or both of the first and second display portions of the dual scan display. The invention thus allows the use of a cursor in a dual scan display environment, without the software overhead associated with conventional software cursor overlaying techniques. The hardware cursor is adaptable to both progressive scan and dual scan type displays, and employs hardware counters for determining where to insert cursor image data into the raster engine video data stream associated with a displayed image, which may include first and second data paths in dual scan mode of operation.
The hardware cursor is adapted to overlay a first portion of the cursor image onto the first display portion and to overlay a second portion of the cursor image onto the second display portion if the cursor crosses the display boundary. For example, first portion cursor data associated with the first portion of the cursor image is inserted into the first data path of the raster engine as the first display portion is scanned out. The second portion cursor data associated with the second portion of the cursor image is then inserted by the hardware cursor apparatus into the second data path of the raster engine. The selective insertion of the first and second portion cursor data may be accomplished via vertical counter with first and second vertical counter values respectively indicating first and second lines of formatted data being rendered to the first and second display portions, and a horizontal counter with a horizontal counter value indicating the column of formatted data being rendered to the display.
Accordingly, the hardware cursor may comprise a first cursor start address register with a first cursor start address indicating a first cursor portion starting line in the first display portion, a second cursor start address register with a second cursor start address indicating a second cursor portion starting line in the second display portion, a first cursor portion height register with a first cursor portion height value indicating a first cursor portion height, a second cursor portion height register with a second cursor portion height value indicating a second cursor portion height, a cursor column register with a cursor column start value, and a cursor image width register with a cursor image width value indicating a cursor image width. A cursor state machine is provided to compare the first vertical counter value with the first cursor start address and the first cursor portion height value, to compare the second vertical counter value with the second cursor start address and the second cursor portion height value, and to compare the horizontal counter value with the cursor column start value and the cursor image width value.
In addition, the hardware cursor may comprise a cursor line buffer adapted to selectively insert first portion cursor data associated with the first portion of the cursor image into the first data path of the raster engine according to the comparison of the first vertical counter value with the first cursor start address and the first cursor portion height value and the comparison of the horizontal counter value with the cursor column start value and the cursor image width value, and to selectively insert second portion cursor data associated with the second portion of the cursor image into the second data path of the raster engine according to the comparison of the second vertical counter value with the second cursor start address and the second cursor portion height value and the comparison of the horizontal counter value with the cursor column start value and the cursor image width value, if the cursor crosses the display boundary.
The invention further provides a method of overlaying a cursor image onto a dual scan display in a video controller for interfacing a frame buffer to a dual scan display having adjacent first and second display portions with a display boundary therebetween, which comprises rendering video data from the frame buffer to the dual scan display using a raster engine, and selectively overlaying a cursor image onto at least one of the first and second display portions according to a cursor position using a hardware cursor. The method may further comprise determining whether the cursor image crosses the display boundary according to the cursor position, determining first and second portions of the cursor image if the cursor image crosses the display boundary, overlaying the first portion of the cursor image onto the first display portion if the cursor crosses the display boundary, and overlaying the second portion of the cursor image onto the second display portion if the cursor crosses the display boundary.
In accordance with still another aspect of the invention, there is provided a raster engine for interfacing a frame buffer in a computer system to a display, which provides programmable support for a variety of disparate display types. The raster engine comprises one or more control registers which are programmable via the computer system to select a display mode. A dual port RAM device is provided to obtain pixel data from the frame buffer, and a multiplexer is provided to select appropriate pixel data from the dual port RAM device according to the selected display mode, and to provide the selected pixel data to an output device according to the selected display mode. In addition, the raster engine comprises a pixel shift logic system with a parallel output, the pixel shift logic system being adapted to receive the pixel data from the multiplexer and to present the selected pixel data at the parallel output according to the selected display mode.
The raster engine is thus programmable to support many different and disparate display types over the same digital interface by formatting and routing color data to the appropriate pins on the interface, which may include a parallel output. Accordingly, interfacing capability is achieved from direct control of LCD row and column drive chips all the way to high definition television (HDTV) size flat panel display types and beyond. Support is also provided for a digital parallel command word interface for low cost displays, such as LCDs and/or VFDs via programmable direct display command interface operation, and YCrCb digital interface to an NTSC encoder for supporting television type displays. In addition, the raster engine may further comprise an integrated digital to analog converter (DAC) to support analog LCD displays and CRTs.
The raster engine may also comprise a look up table, a grayscale generator, and a blink logic system, wherein the multiplexer receives the selected pixel data from the dual port RAM device via the one of the look up table, the grayscale generator, and the blink logic system. The pixel shift logic system may be adapted to present the selected pixel data in a 24 bit parallel format when the selected display mode is one of single 16 bit 565 pixels per clock and single 16 bit 555 pixels per clock. In achieving the appropriate routing of video output signals for such universal display type interfacing, the pixel shift logic system may be adapted to copy a plurality of most significant bits from the selected pixel data into a corresponding plurality of unused least significant bits in the 24 bit parallel format.
Thus, whereas conventional raster engines and video controllers required manual rerouting of signal connections to interface different display formats, the present invention provides universal connectivity via the novel signal translation using the pixel shift logic system. In addition, the raster engine provides programmable support for both progressive scan and dual scan type displays according to the selected display mode. The display mode may comprise shift mode and pixel mode settings programmable via one or more control registers. For example, the shift mode may comprise one of single pixel per pixel clock up to 24 bits wide, single 24 or 16 bit pixel per pixel clock mapped to 18 bits, 2 pixels per shift clock up to 9 bits wide, 4 pixels per shift clock up to 4 bits wide, 8 pixels per shift clock up to 2 bits wide, 2⅔ 3 bit pixels per clock over 8 bit bus, dual scan 2⅔ 3 bit pixels per clock over two 8 bit busses, and 1 pixel per pixel clock. In addition, the pixel mode may comprise one of 4 bits per pixel, 8 bits per pixel, 16 bits per pixel, 24 bits per pixel, or 32 bits per pixel.
In accordance with yet another aspect of the present invention, there is provided a video controller for interfacing a frame buffer to a display in a computer system, which comprises a raster engine adapted to receive video data from the frame buffer, to format the video data, and to render the formatted data to the display, as well as a hardware blink logic system operatively associated with the raster engine to selectively blink at least one pixel on the display. A blink mode control register may be operatively associated with the hardware blink logic system and programmable via the computer system to select a blink mode, wherein the hardware blink logic system is adapted to selectively blink at least one pixel on the display according to the selected blink mode. The provision of a hardware blink logic system eliminates the overhead associated with conventional software intensive blinking techniques such as redrawing blinking objects continuously or drawing a blinked and unblinked frame for the hardware to switch between, and further provides for selective blinking of individual pixels, heretofore not achieved in hardware blinking systems.
The selected blink mode may comprise one of pixels ANDed with blink mask, pixels ORed with blink mask, pixels XORed with blink mask, blink to background, blink to offset color single value mode, blink to offset color 888 mode, blink dimmer, blink brighter, blink dimmer 888 mode, blink brighter 888 mode, and blink mode disabled, wherein the xe2x80x98888xe2x80x99 modes comprise 3 bits each for the colors red, green, and blue, and wherein separate mathematical operations may be performed separately for each such color channel. The hardware further identifies blinking pixels according to the formatted data, and selectively blinks one or more blinking pixels on the display according to the selected blink mode. A blink mask control register may be provided, which is programmable in order to select a blink mask. For some blink modes, the hardware blink logic system may accordingly blink the blinking pixel or pixels on the display according to the selected blink mode and the selected blink mask.
For example, the blink logic system may selectively perform a logical AND, OR, or exclusive OR (XOR) operation on formatted data associated with the blinking pixels using the selected blink mask, in order to change the color or shading of the blinking pixels in the blink state in a programmatically controlled fashion. This flexibility allows high quality display of blinking pixels not limited to a single blink color (e.g., blink to background color) as was common in the past. Blink to background color operation is supported along with blinking to an offset, as well as blinking brighter and/or blinking dimmer. Multiple blinking rates and duty cycles may be further programmed via a blink rate control register in the raster engine.
In accordance with still another aspect of the invention, there is provided a raster engine for interfacing a frame buffer in a computer system to one of a plurality of disparate displays, which comprises a control register programmable via the computer system to select a display mode, a dual port RAM device operative to obtain pixel data from the frame buffer, and a logic device having a parallel output, the logic device being adapted to select appropriate pixel data from the dual port RAM device according to the selected display mode, to remap the selected pixel data according to the selected display mode, and to provide the remapped selected pixel data at the parallel output according to a universal routing scheme applicable to multiple disparate display types. The raster engine remaps the pixel data from the frame buffer format to an output format required by a selected display type according to a universal routing scheme, without requiring any rerouting of signals outside the raster engine. The raster engine thus provides programmable support for a plurality of color depth application programs, as well as interfacing thereof with a plurality of disparate displays having varying color depth capabilities, wherein the color depth refers to the number of bits per pixel.
For example, the raster engine display mode may comprise single pixel per clock up to 24 bits wide, single 16 bit 565 pixel per clock, single 16 bit 555 pixel per clock, single 24 bit pixel on 18 lines, single 16 bit 565 pixel on 18 lines, single 16 bit 555 pixel on 18 lines, 2 pixels per clock, 4 pixels per clock, 8 pixels per shift clock, 2⅔ pixels per clock, and/or dual 2⅔ pixels per clock. The raster engine may further comprise a look up table (LUT), a grayscale generator, and a blink logic system, wherein the logic device receives the selected pixel data from the dual port RAM device via the one of the LUT, the grayscale generator, and the blink logic system according to the selected display mode. Thus, the raster engine may programmatically combine grayscaling, blinking, and color translation functionality via one or more programmable control registers. In this regard, the logic device may comprise a multiplexer.
The logic device may be further adapted to copy a plurality of most significant bits from the selected pixel data into a corresponding plurality of unused least significant bits in the 24 bit parallel format, whereby improved color intensity range is provided. Thus, where a translation from an application program having one color depth to a display type having a different color depth capability, the logic device ensures maximum available color capability utilization. The display mode selected via the control register may comprise a color mode, a shift mode, and a pixel mode, wherein the color mode comprises one of a look up table mode, triple 8 bits per channel, 16 bit 565 color mode, 16 bit 555 color mode, and a grayscale palette enabled mode. The logic device is thus adapted to translate the selected pixel data from a first format to a second format according to the selected display mode. In addition, where certain bits in the selected pixel data may otherwise be unused, the raster engine may selectively interpolate between a portion of the selected pixel data in the first format to generate a portion of the data in the second format. For example, the logic device may perform a logical OR combination of at least two bits of the selected pixel data in the first format to generate a bit in the second format.
In accordance with yet another aspect of the present invention, there is provided a raster engine for interfacing a frame buffer in a computer system to one of a plurality of disparate display types, comprising a control register programmable via the computer system to select a display mode, a grayscale generator operative to obtain pixel data from the frame buffer and programmable via the computer system to generate grayscale formatted data according to the selected display mode, and a logic device having a parallel output, the logic device being adapted to select appropriate pixel data from the grayscale generator according to the selected display mode, and to provide the selected pixel data at the parallel output according to the selected display mode.
The raster engine may further comprise a grayscale look up table control register programmable by the computer system, and a grayscale look up table programmable by the computer system via the grayscale look up table control register. The grayscale generator may further comprise a frame counter, a vertical counter, and a horizontal counter, wherein the grayscale look up table data entries define dithering operation for a pixel value according to the frame counter, the vertical counter, and the horizontal counter. The invention thus provides a grayscale look up table or matrix which is programmable by a user or an application program in order to effectively provide flexible interfacing to low cost display panels, such as monochrome, LCD, and electro-luminescent (EL) displays.
According to another aspect of the invention, the raster engine may provide an indication to a host processor that the raster engine is underflowing or about to underflow. Input and output counters in the raster engine first in first out (FIFO) memory, which interfaces the host bus with the raster engine video systems, are read by an underflow detection system which is adapted to provide an underflow indication according to the counter values. The underflow detection and indication system thus minimizes or reduces the undesirable visual effects associated with a starved or empty raster engine.